preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. december 2006 rev 2 1/9 9 STK802 n-channel 30v - 0.0019 ? - 34a - polarpak ? stripfet? power mosfet general features ultra low top and bottom junction to case thermal resistance very low on resistance 100% rg tested fully incapsulated die in compliance with the 2002/95/ec european directive polarpak ? is a registered trademark of vishay description this power mosfet is the latest development of stmicroelectronics unique ?single feature size?? strip-based process. the resulting transistor shows extremely high packing density for low on- resistance, moreover the double sides cooling package with ultra low junction to case thermal resistance allows to handle higher levels of current. applications switching application internal schematic diagram type v dss r ds(on) r ds(on) *q g p tot STK802 30v <0.0025 ? 105.6nc*m ? 5.2w polarpak ? bottom view top view www.st.com order codes part number marking package packaging STK802 k802 polarpak ? tape & reel
electrical ratings STK802 2/9 1 electrical ratings table 1. absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v gs (1) 1. continuous mode gate-source voltage 16 v v gs (2) 2. guaranteed for test time < 15ms gate-source voltage 18 v i d (4) drain current (continuous) at t c = 25c 34 a i d drain current (continuous) at t c = 100c 21 a i dm (3) 3. pulse width limited by package drain current (pulsed) 136 a p tot (4) 4. when mounted on fr-4 board of 1inch 2 , 2 oz cu and 10sec total dissipation at t c = 25c 5.2 w derating factor 0.0416 w/c t j t stg operating junction temperature storage temperature -55 to 150 c table 2. thermal data symbol parameter typ. max. unit rthj-amb (1) 1. when mounted on fr-4 board of 1inch 2 , 2 oz cu and 10sec thermal resistance junction-amb 20 24 c/w rthj-c (2) 2. steady state thermal resistance junction-case (top drain) 0.8 1 c/w rthj-c (3) 3. measured at source pin when the device is mounted on fr-4 board in steady state thermal resistance junction-case (source) 2.2 2.7 c/w
STK802 electrical characteristics 3/9 2 electrical characteristics (t case =25c unless otherwise specified) table 3. on/off symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating, v ds = max rating,tc=125c 1 10 a a i gss gate body leakage current (v ds = 0) v gs = 16v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250a 12.5v r ds(on) static drain-source on resistance v gs = 10v, i d = 17a v gs = 4.5v, i d = 17a 0.0019 0.0024 0.0025 0.0031 ? ? table 4. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25v, f=1 mhz, v gs =0 5940 890 67 pf pf pf q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =15v, i d = 34a v gs =4.5v (see figure 2) 44 tbd tbd nc nc nc
electrical characteristics STK802 4/9 table 5. switching times symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 15v, i d = 17a, r g =4.7 ?, v gs =4.5v (see figure 1) tbd tbd ns ns t d(off) t f turn-off delay time fall time v dd =15v, i d = 17a, r g =4.7 ?, v gs =4.5v (see figure 1) tbd tbd ns ns table 6. source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm (1) 1. pulse width limited by package source-drain current source-drain current (pulsed) 34 136 a a v sd (2) 2. pulsed: pulse duration = 300s, duty cycle 1.5% forward on voltage i sd = 17a, v gs =0 1.2 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 34a, di/dt = 100a/s, v dd =20v, tj=150c (see figure 6) tbd tbd tbd ns nc a
STK802 test circuits 5/9 3 test circuits figure 1. switching times test circuit for resistive load figure 2. gate charge test circuit figure 3. test circuit for inductive load switching and diode recovery times figure 4. unclamped inductive load test circuit figure 5. unclamped inductive wavefo rm figure 6. switching time waveform
package mechanical data STK802 6/9 4 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
STK802 package mechanical data 7/9 ref. mm inch min. typ. max. min. typ. max. a 0.75 0.80 0.85 0.030 0.031 0.033 a1 0.05 0.002 b1 0.48 0.58 0.68 0.019 0.023 0.027 b2 0.41 0.51 0.61 0.016 0.020 0.024 b3 2.19 2.29 2.39 0.086 0.090 0.094 b4 0.89 1.04 1.19 0.035 0.041 0.047 b5 0.23 0.33 0.43 0.009 0.013 0.017 c 0.20 0.25 0.30 0.008 0.010 0.012 d 6 6.15 6.30 0.236 0.242 0.248 d1 5.74 5.89 6.04 0.226 0.232 0.238 e 5.01 5.16 5.31 0.197 0.203 0.209 e1 4.75 4.90 5.05 0.187 0.193 0.199 h1 0.23 0.009 h2 0.45 0.56 0.020 0.022 h3 0.31 0.41 0.51 0.012 0.016 0.020 h4 0.45 0.56 0.020 0.022 k1 4.22 4.37 4.52 0.166 0.172 0.178 k2 1.08 1.13 1.18 0.043 0.044 0.046 k3 1.37 0.054 k4 0.24 0.009 m1 4.30 4.50 4.70 0.169 0.177 0.185 m2 3.43 3.58 3.73 0.135 0.141 0.147 m3 0.22 0.009 m4 0.05 0.002 p1 0.15 0.20 0.25 0.006 0.008 0.010 t1 3.48 3.64 4.10 0.137 0.143 0.150 t2 0.56 0.76 0.95 0.22 0.030 0.037 t3 1.20 0.051 t4 3.90 0.154 t5 0.18 0.36 0.007 0.014 < 0 10 12 0 10 12 polarpak ? (option ?l?) mechanical data
revision history STK802 8/9 5 revision history table 7. revision history date revision changes 10-oct-2006 1 first version 19-dec-2006 2 small text changes, update test conditions ( table 1. , table 3. , table 4. , ta bl e 5 . , table 6. )
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